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CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV
3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM
Features

Fully asynchronous operation Automatic power down Expandable data bus to 32 bits, 36 bits or more using Master and Slave chip select when using more than one device On chip arbitration logic Semaphores included to permit software handshaking between ports INT flag for port-to-port communication Separate upper byte and lower byte control Pin select for Master or Slave (M/S) Commercial and industrial temperature ranges Available in 100-pin Pb-free TQFP and 100-pin TQFP
True dual-ported memory cells which enable simultaneous access of the same memory location 4, 8 or 16K x 16 organization (CY7C024AV/024BV [1]/ 025AV/026AV) 4 or 8K x 18 organization (CY7C0241AV/0251AV) 16K x 18 organization (CY7C036AV) 0.35 micron CMOS for optimum speed and power High speed access: 20 and 25 ns Low operating power Active: ICC = 115 mA (typical) Standby: ISB3 = 10 A (typical)
Logic Block Diagram
R/WL UBL R/WR UBR
CEL LBL OEL
CER LBR OER
[2]
IO8/9L-IO15/17L
[3] IO0L-IO7/8L
[2]
8/9 8/9
8/9
IO Control
IO Control
8/9
IO8/9L-IO15/17R
[3]
IO0L-IO7/8R
A0L-A11/1213L
[4]
12/13/14
Address Decode
12/13/14
True Dual-Ported RAM Array
Address Decode
12/13/14
12/13/14
A0R-A11/12/13R
[4]
[4]
[4]
A0L-A11/12/13L CEL OEL R/WL SEML [5] BUSYL INTL UBL LBL
Notes 1. CY7C024AV and CY7C024BV are functionally identical. 2. IO8-IO15 for x16 devices; IO9-IO17 for x18 devices. 3. IO0-IO7 for x16 devices; IO0-IO8 for x18 devices. 4. A0-A11 for 4K devices; A0-A12 for 8K devices; A0-A13 for 16K devices. 5. BUSY is an output in master mode and an input in slave mode.
Interrupt Semaphore Arbitration
A0R-A11/12/13R CER OER R/WR SEMR
[5]
M/S
BUSYR INTR UBR LBR
Cypress Semiconductor Corporation Document #: 38-06052 Rev. *J
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised December 10, 2008
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CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV
Pin Configurations
Figure 1. 100-Pin TQFP (Top View)
OEL VCC R/W L SEML CEL
UBL LBL NC [6] A11L A10L
IO 4L IO 3L IO 2L GND
IO 9L IO 8L IO 7L IO 6L IO 5L
IO 1L IO 0L
A9L A8L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC NC NC NC IO 10L IO 11L IO 12L IO 13L GND IO 14L IO 15L VCC GND IO 0R IO 1R IO 2R VCC IO 3R IO 4R IO 5R IO 6R NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC NC NC NC A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R NC NC NC NC
CY7C024AV/024BV (4K x 16) CY7C025AV (8K x 16)
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
IO 7R IO 8R IO 9R IO 10R IO 11R IO 12R IO 13R IO 14R GND IO 15R OER
R\WR GND SEMR CER UBR LBR NC[7] A11R A10R A9R A8R
Notes 6. A12L on the CY7C025AV. 7. A12R on the CY7C025AV.
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A7R A6R A5R
A7L A6L
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Pin Configurations (continued)
Figure 2. 100-Pin TQFP (Top View)
IO 10L IO 9L IO 7L IO 6L IO 5L UBL LBL NC [8] A11L A10L OEL VCC R/WL SEML CEL IO 4L IO 3L IO 2L GND IO 1L IO 0L A9L A8L A7L A6L 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC NC IO 8L IO 17L IO 11L IO 12L IO 13L IO 14L GND IO 15L IO 16L VCC GND IO 0R IO 1R IO 2R VCC IO 3R IO 4R IO 5R IO 6R IO 8R IO 17R NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 NC NC NC NC A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R NC NC NC NC
CY7C0241AV (4K x 18) CY7C0251AV (8K x 18)
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC NC NC NC IO10L IO11L IO12L IO13L GND IO14L IO15L VCC GND IO0R IO1R IO2R VCC IO3R IO4R IO5R IO6R NC NC NC NC 75 1 74 2 73 3 72 4 71 5 70 6 69 7 68 8 67 9 66 10 65 11 64 12 63 13 62 14 61 15 60 16 59 17 18 58 19 57 20 56 21 55 22 54 23 53 24 52 25 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC NC NC A6L A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R A5R NC NC NC
IO15R OER R/WR GND SEMR CER
IO7R IO8R IO9R IO10R IO11R IO12R
IO13R IO14R GND
UBR LBR A13R A12R A11R A10R
Notes 8. A12L on the CY7C0251AV. 9. A12R on the CY7C0251AVC.
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A9R A8R A7R A6R
IO 10R IO 11R IO 12R IO 13R IO 14R IO 15R GND IO1L IO 16R OER IO0L OEL R/WR GND VCC SEMR R/WL CER SEML UBR CEL LBR UBL NC [9] LBL A11R A13L A10R A12L A9R A11L A8R A10L A7R A9L A6R A8L A5R A7L
IO9L IO8L IO7L IO6L IO5L IO4L IO3L IO2L GND
IO 7R IO 9R
CY7C026AV (16K x 16)
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Pin Configurations (continued)
Figure 3. 100-Pin TQFP (Top View)
IO 10L IO 9L IO 7L IO 6L IO 5L OEL VCC R/WL SEML CEL IO 4L IO 3L IO 2L GND IO 1L IO 0L UBL LBL A12L A11L A10L A9L A8L A7L A6L 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC NC IO 8L IO 17L IO 11L IO 12L IO 13L IO 14L GND IO 15L IO 16L VCC GND IO 0R IO 1R IO 2R VCC IO 3R IO 4R IO 5R IO 6R IO 8R IO 17R NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 NC NC NC A13L A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R A13R NC NC NC
CY7C036AV (16K x 18)
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
IO 7R IO 9R IO 10R IO 11R IO 12R IO 13R IO 14R IO 15R GND IO 16R OER R/WR GND SEMR CER UBR LBR A12R A11R A10R A9R A8R
Selection Guide
Parameter Maximum Access Time Typical Operating Current Typical Standby Current for ISB1 (Both ports TTL Level) Typical Standby Current for ISB3 (Both ports CMOS Level) CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV -20 20 120 35 10 CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV -25 25 115 30 10 Unit ns mA mA A
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A7R A6R A5R
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Pin Definitions
Left Port CEL R/WL OEL A0L-A13L IO0L-IO17L SEML UBL LBL INTL BUSYL M/S VCC GND NC Right Port CER R/WR OER A0R-A13R IO0R-IO17R SEMR UBR LBR INTR BUSYR Chip Enable Read and Write Enable Output Enable Address (A0-A11 for 4K devices; A0-A12 for 8K devices; A0-A13 for 16K) Data Bus Input and Output Semaphore Enable Upper Byte Select (IO8-IO15 for x16 devices; IO9-IO17 for x18 devices) Lower Byte Select (IO0-IO7 for x16 devices; IO0-IO8 for x18 devices) Interrupt Flag Busy Flag Master or Slave Select Power Ground No Connect accessed by the other port. The Interrupt flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic has eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power down feature is controlled independently on each port by a Chip Select (CE) pin. The CY7C024AV/024BV/025AV/026AV and CY7C0241AV0251AV/036AV are available in 100-pin Pb-free Thin Quad Flat Pack (TQFP) and 100-pin TQFP. Description
Architecture
The CY7C024AV/024BV/025AV/026AV and CY7C0241AV/0251AV/036AV consist of an array of 4K, 8K, and 16K words of 16 and 18 bits each of dual-port RAM cells, IO and address lines, and control signals (CE, OE, RW). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes and reads to the same location, a BUSY pin is provided on each port. Two Interrupt (INT) pins can be used for port to port communication. Two Semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the devices can function as a master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). They also have an automatic power down feature controlled by CE. Each port has its own output enable control (OE), which enables data to be read from the device.
Write Operation
Data must be set up for a duration of tSD before the rising edge of RW to guarantee a valid write. A write operation is controlled by either the RW pin (see Figure 8 on page 12) or the CE pin (see Figure 9 on page 12). Required inputs for non-contention operations are summarized in Table 1 on page 7. If a location is being written to by one port and the opposite port tries to read that location, there must be a port to port flowthrough delay before the data is read on the output; otherwise the data read is not deterministic. Data is valid on the port tDDD after the data is presented on the other port.
Functional Description
The CY7C024AV/024BV/025AV/026AV and CY7C0241AV/0251AV/036AV are low power CMOS 4K, 8K, and 16K x16/18 dual port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. There are two ports permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be used as standalone 16 or18-bit dual port static RAMs or multiple devices can be combined to function as a 32 or 36-bit or wider master and slave dual port static RAM. An M/S pin is provided for implementing 32 or 36-bit or wider memory applications. It does not need separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual port video and graphics memory. Each port has independent control pins: Chip Enable (CE), Read or Write Enable (R/W), and Output Enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being Document #: 38-06052 Rev. *J
Read Operation
When reading the device, the user must assert both the OE and CE pins. Data is available tACE after CE or tDOE after OE is asserted. If the user wants to access a semaphore flag, then the SEM pin and OE must be asserted.
Interrupts
The upper two memory locations are for message passing. The highest memory location (FFF for the CY7C024AV/024BV/41AV/1FFF for the CY7C025AV/51AV,
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3FFF for the CY7C026AV/36AV) is the mailbox for the right port and the second highest memory location (FFE for the CY7C024AV/024BV/41AV/1FFE for the CY7C025AV/51AV, 3FFE for the CY7C026AV/36AV) is the mailbox for the left port. When one port writes to the other port's mailbox, an interrupt is generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox. The message is user defined. Each port can read the other port's mailbox without resetting the interrupt. The active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. Also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. If an application does not require message passing, do not connect the interrupt pin to the processor's interrupt request input pin. The operation of the interrupts and their interaction with Busy are summarized in Table 2 on page 7.
Semaphore Operation
The CY7C024AV/024BV/025AV/026AV and CY7C0241AV/0251AV/036AV provide eight semaphore latches, which are separate from the dual port memory locations. Semaphores are used to reserve resources that are shared between the two ports. The state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. The left port then verifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tSOP before attempting to read the semaphore. The semaphore value is available tSWRD + tDOE after the rising edge of the semaphore write. If the left port was successful (reads a zero), it assumes control of the shared resource. Otherwise (reads a one), it assumes the right port has control and continues to poll the semaphore. When the right side has relinquished control of the semaphore (by writing a one), the left side succeeds in gaining control of the semaphore. If the left side no longer requires the semaphore, a one is written to cancel its request. Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip select for the semaphore latches (CE must remain HIGH during SEM LOW). A0-2 represents the semaphore address. OE and RW are used in the same manner as a normal memory access. When writing or reading a semaphore, the other address pins have no effect. When writing to the semaphore, only IO0 is used. If a zero is written to the left port of an available semaphore, a one appears at the same semaphore address on the right port. That semaphore can now only be modified by the side showing zero (the left port in this case). If the left port now relinquishes control by writing a one to the semaphore, the semaphore is set to one for both sides. However, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. Table 3 on page 7 shows sample semaphore operations. When reading a semaphore, all 16 and 18 data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. If both ports attempt to access the semaphore within tSPS of each other, the semaphore is definitely obtained by one of them. But there is no guarantee which side controls the semaphore.
Busy
The CY7C024AV/024BV/025AV/026AV and CY7C0241AV/0251AV/036AV provide on-chip arbitration to resolve simultaneous memory location access (contention). If both ports' CEs are asserted and an address match occurs within tPS of each other, the busy logic determines which port has access. If tPS is violated, one port definitely gains permission to the location, but it is not predictable which port gets that permission. BUSY is asserted tBLA after an address match or tBLC after CE is taken LOW.
Master/Slave
A M/S pin helps to expand the word width by configuring the device as a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. This enables the device to interface to a master device with no external components. Writing to slave devices must be delayed until after the BUSY input has settled (tBLC or tBLA). Otherwise, the slave chip may begin a write cycle during a contention situation. When tied HIGH, the M/S pin enables the device to be used as a master and, therefore, the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave.
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Table 1. Non-Contending Read/Write Inputs CE H X L L L L L L X H X H X L L X X R/W X X L L L H H H X H H OE X X X X X L L L H L L X X X X UB X H L H L L H L X X H X H L X LB X H H L L H L L X X H X H X L SEM H H H H H H H H X L L L L L L IO9-IO17 High Z High Z Data In High Z Data In Data Out High Z Data Out High Z Data Out Data Out Data In Data In Outputs IO0-IO8 High Z High Z High Z Data In Data In High Z Data Out Data Out High Z Data Out Data Out Data In Data In Operation Deselected: Power Down Deselected: Power Down Write to Upper Byte Only Write to Lower Byte Only Write to Both Bytes Read Upper Byte Only Read Lower Byte Only Read Both Bytes Outputs Disabled Read Data in Semaphore Flag Read Data in Semaphore Flag Write DIN0 into Semaphore Flag Write DIN0 into Semaphore Flag Not Allowed Not Allowed
Table 2. Interrupt Operation Example (assumes BUSYL = BUSYR = HIGH)[10] Left Port Function Set Right INTR Flag Reset Right INTR Flag Set Left INTL Flag Reset Left INTL Flag R/WL L X X X CEL L X X L OEL X X X L A0L-13L FFF[13] X X 1FFE[13] INTL X X L[11] H[12] R/WR X X L X CER X L L X Right Port OER X L X X A0R-13R X FFF (or 1/3FFF) 1FFE (or 1/3FFE) X INTR L[12] H[11] X X
Table 3. Semaphore Operation Example Function No action Left port writes 0 to semaphore Right port writes 0 to semaphore Left port writes 1 to semaphore Left port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 1 to semaphore Right port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 0 to semaphore Left port writes 1 to semaphore IO0-IO17 Left 1 0 0 1 1 0 1 1 1 0 1 IO0-IO17 Right 1 1 1 0 0 1 1 0 1 1 1 Semaphore-free Left Port has semaphore token No change. Right side has no write access to semaphore Right port obtains semaphore token No change. Left port has no write access to semaphore Left port obtains semaphore token Semaphore-free Right port has semaphore token Semaphore free Left port has semaphore token Semaphore-free Status
Notes 10. See Functional Description on page 5 for specific highest memory locations by device. 11. If BUSYR=L, then no change. 12. If BUSYL=L, then no change. 13. See Functional Description on page 5 for specific addresses by device.
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Maximum Ratings
Exceeding maximum ratings[14] may shorten the useful life of the device. User guidelines are not tested. Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................ -55C to +125C Supply Voltage to Ground Potential............... -0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State ......................... -0.5V to VCC + 0.5V DC Input Voltage[15] ............................... -0.5V to VCC + 0.5V Output Current into Outputs (LOW) ............................. 20 mA Static Discharge Voltage.......................................... > 2001V Latch-up Current.................................................... > 200 mA
Operating Range
Range Commercial Industrial[16] Ambient Temperature 0C to +70C -40C to +85C VCC 3.3V 300 mV 3.3V 300 mV
Electrical Characteristics
Over the Operating Range CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Parameter Description Min VOH VOL VIH VIL IOZ IIX ICC ISB1 ISB2 ISB3 ISB4 Output HIGH Voltage (VCC=3.3V) Output LOW Voltage Input HIGH Voltage Input LOW Voltage Output Leakage Current Input Leakage Current Operating Current (VCC = Max., IOUT = 0 mA) Outputs Disabled Standby Current (Both Ports TTL Level) CEL & CER VIH, f = fMAX Standby Current (One Port TTL Level) CEL | CER VIH, f = fMAX Com'l. Ind.[16] Com'l. Ind.
[16]
-20 Typ Max 0.4 2.0 -0.3[17] -10 -10 120 35 75 10 70 0.8 10 10 175 45 110 500 95 -10 -10 2.0 Min 2.4 2.4
-25 Typ Max
Unit
V 0.4 0.8 10 10 115 135 30 40 65 75 10 10 60 70 165 185 40 50 95 105 500 500 80 90 V V V A A mA mA mA mA mA mA A A mA mA
Com'l. Ind.[16]
Standby Current (Both Ports CMOS Level) Com'l. CEL & CER VCC-0.2V, f = 0 Ind.[16] Standby Current (One Port CMOS Level) CEL | CER VIH, f = fMAX[18] Com'l. Ind.
[16]
Capacitance
Parameter[19] CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max 10 10 Unit pF pF
Notes 14. The voltage on any input or IO pin cannot exceed the power pin during power up. 15. Pulse width < 20 ns. 16. Industrial parts are available in CY7C026AV and CY7C036AV only. 17. VIL > -1.5V for pulse width less than 10ns. 18. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3. 19. Tested initially and after any design or process changes that may affect these parameters.
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Figure 4. AC Test Loads and Waveforms
3.3V 3.3V R1 = 590 OUTPUT C = 30 pF R2 = 435 VTH = 1.4V OUTPUT C = 30pF RTH = 250 R1 = 590 OUTPUT C = 5 pF R2 = 435
(a) Normal Load (Load 1)
(b) Thevenin Equivalent (Load 1) ALL INPUT PULSES
3.0V GND 10% 3 ns 90% 90% 10% 3 ns
(c) Three-State Delay (Load 2) (Used for tLZ, tHZ, tHZWE, and tLZWE including scope and jig)
Switching Characteristics
Over the Operating Range [20] CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Parameter Description Min Read Cycle tRC tAA tOHA tACE[21] tDOE tLZOE[22, 23, 24] tHZOE[22, 23, 24] tLZCE[22, 23, 24] tHZCE[22, 23, 24] tPU[24] tPD[24] tABE[21] Write Cycle tWC tSCE[21] tAW tHA tSA[21] Write Cycle Time CE LOW to Write End Address Valid to Write End Address Hold From Write End Address Setup to Write Start 20 15 15 0 0 25 20 20 0 0 ns ns ns ns ns Read Cycle Time Address to Data Valid Output Hold From Address Change CE LOW to Data Valid OE LOW to Data Valid OE Low to Low Z OE HIGH to High Z CE LOW to Low Z CE HIGH to High Z CE LOW to Power Up CE HIGH to Power Down Byte Enable Access Time 0 20 20 3 12 0 25 25 3 12 3 15 3 20 12 3 15 20 20 3 25 13 25 25 ns ns ns ns ns ns ns ns ns ns ns ns -20 Max Min -25 Max Unit
Notes 20. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOI/IOH and 30 pF load capacitance. 21. To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time. 22. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 23. Test conditions used are Load 3. 24. This parameter is guaranteed but not tested. For information on port to port delay through RAM cells from writing port to reading port, refer to Figure 12.
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Switching Characteristics
Over the Operating Range (continued)[20] CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Parameter Description Min tPWE tSD tHD tHZWE[23, 24] tLZWE[23, 24] tWDD[25] tDDD[25] Busy tBLA tBHA tBLC tBHC tPS tWB tWH tBDD[27] tINS tINR tSOP tSWRD tSPS tSAA Timing[26] BUSY LOW from Address Match BUSY HIGH from Address Mismatch BUSY LOW from CE LOW BUSY HIGH from CE HIGH Port Setup for Priority R/W HIGH after BUSY (Slave) R/W HIGH after BUSY HIGH (Slave) BUSY HIGH to Data Valid INT Set Time INT Reset Time SEM Flag Update Pulse (OE or SEM) SEM Flag Write to Read Time SEM Flag Contention Window SEM Address Access Time 10 5 5 20 5 0 15 20 20 20 12 5 5 25 20 20 20 17 5 0 17 25 20 20 20 20 20 17 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Write Pulse Width Data Setup to Write End Data Hold From Write End R/W LOW to High Z R/W HIGH to Low Z Write Pulse to Data Delay Write Data Valid to Read Data Valid 3 45 30 15 15 0 12 0 50 35 -20 Max Min 20 15 0 15 -25 Max ns ns ns ns ns ns ns Unit
Interrupt Timing[26]
Semaphore Timing
Data Retention Mode
The CY7C024AV/024BV/025AV/026AV and CY7C0241AV/0251AV/036AV are designed for battery backup. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip Enable (CE) must be held HIGH during data retention, within VCC to VCC - 0.2V. 2. CE must be kept between VCC - 0.2V and 70 percent of VCC during the power up and power down transitions. 3. The RAM can begin operation >tRC after VCC reaches the minimum operating voltage (3.0V).
Timing
Data Retention Mode VCC 3.0V VCC > 2.0V 3.0V tRC
V IH
CE
VCC to VCC - 0.2V
Parameter ICCDR1
Notes 25. For information on port to port delay through RAM cells from writing port to reading port, refer to Figure 12. 26. Test conditions used are Load 2. 27. tBDD is a calculated parameter and is the greater of tWDD - tPWE (actual) or tDDD - tSD (actual). 28. CE = VCC, Vin = GND to VCC, TA = 25C. This parameter is guaranteed but not tested.
Test Conditions[28] at VCCDR = 2V
Max 50
Unit A
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Switching Waveforms
Figure 5. Read Cycle No. 1 (Either Port Address Access)[29, 30, 31]
tRC ADDRESS tOHA DATA OUT tAA DATA VALID tOHA
PREVIOUS DATA VALID
Figure 6. Read Cycle No. 2 (Either Port CE/OE Access)[29, 32, 33]
CE and LB or UB OE tLZOE DATA OUT tLZCE tPU ICC CURRENT ISB tPD DATA VALID tACE tHZCE tDOE tHZOE
Figure 7. Read Cycle No. 3 (Either Port)[29, 31, 32, 33]
tRC ADDRESS tAA UB or LB tHZCE tLZCE tABE CE tACE tLZCE DATA OUT tHZCE tOHA
Notes 29. R/W is HIGH for read cycles. 30. Device is continuously selected CE = VIL and UB or LB = VIL. This waveform cannot be used for semaphore reads. 31. OE = VIL. 32. Address valid prior to or coincident with CE transition LOW. 33. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.
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Switching Waveforms (continued)
Figure 8. Write Cycle No. 1: R/W Controlled Timing[34, 35, 36, 37]
tWC ADDRESS tHZOE [40] OE tAW CE
[38, 39]
tSA R/W tHZWE[40] DATA OUT NOTE 41
tPWE[37]
tHA
tLZWE NOTE 41 tSD tHD
DATA IN
Figure 9. Write Cycle No. 2: CE Controlled Timing[34, 35, 36, 42]
tWC ADDRESS tAW CE
[38, 39]
tSA R/W
tSCE
tHA
tSD DATA IN
tHD
Notes 34. R/W or CE must be HIGH during all address transitions. 35. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB. 36. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle. 37. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to enable the IO drivers to turn off and data to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE. 38. To access RAM, CE = VIL, SEM = VIH. 39. To access upper byte, CE = VIL, UB = VIL, SEM = VIH. To access lower byte, CE = VIL, LB = VIL, SEM = VIH. 40. Transition is measured 500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100 percent tested. 41. During this period, the IO pins are in the output state, and input signals must not be applied. 42. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.
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Switching Waveforms (continued)
Figure 10. Semaphore Read After Write Timing, Either Side[43]
tSAA A 0-A 2 VALID ADRESS tAW SEM tSCE tSD IO 0 tSA R/W tSWRD OE WRITE CYCLE tSOP READ CYCLE tDOE DATAIN VALID tPWE tHD DATAOUT VALID tHA tSOP VALID ADRESS tACE tOHA
Figure 11. Timing Diagram of Semaphore Contention[44, 45, 46]
A0L -A2L
MATCH
R/WL SEM L tSPS A 0R -A 2R MATCH
R/WR SEM R
Notes 43. CE = HIGH for the duration of the above timing (both write and read cycle). 44. IO0R = IO0L = LOW (request semaphore); CER = CEL = HIGH. 45. Semaphores are reset (available to both ports) at cycle start. 46. If tSPS is violated, the semaphore is definitely obtained by one side or the other, but which side gets the semaphore is unpredictable.
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Switching Waveforms (continued)
Figure 12. Timing Diagram of Read with BUSY (M/S=HIGH)[47]
tWC ADDRESSR R/WR MATCH tPWE
tSD DATA INR tPS ADDRESSL MATCH tBLA BUSYL tDDD DATA OUTL tWDD VALID
tHD
tBHA tBDD
VALID
Figure 13. Write Timing with Busy Input (M/S=LOW)
R/W tWB tPWE
BUSY
tWH
Note 47. CEL = CER = LOW.
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Switching Waveforms (continued)
Figure 14. Busy Timing Diagram No.1 (CE Arbitration)[48] CELValid First
ADDRESS L,R CEL tPS CER tBLC BUSYR tBHC ADDRESS MATCH
CER Valid First:
ADDRESS L,R CER tPS CE L tBLC BUSY L tBHC ADDRESS MATCH
Figure 15. Busy Timing Diagram No.2 (Address Arbitration)[48] Left Address Valid First:
tRC or tWC ADDRESS L ADDRESS MATCH tPS ADDRESSR tBLA BUSY R tBHA ADDRESS MISMATCH
Right Address Valid First:
tRC or tWC ADDRESSR ADDRESS MATCH tPS ADDRESSL tBLA BUSY L
Note 48. If tPS is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side BUSY is asserted.
ADDRESS MISMATCH
tBHA
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Switching Waveforms (continued)
Figure 16. Interrupt Timing Diagram Left Side Sets INTR :
ADDRESSL CE L R/W L INT R tINS [50] tWC WRITE 1FFF (OR 1/3FFF) tHA[49]
Right Side Clears INT R :
ADDRESSR CE R tINR [50] R/WR OE R INTR
tRC READ 7FFF (OR 1/3FFF)
Right Side Sets INT L:
tWC ADDRESSR CE R R/W R INT L tINS
[50]
WRITE 1FFE (OR 1/3FFE) tHA[49]
Left Side Clears INT L:
ADDRESSR CE L tINR[50] R/W L OE L INT L
Notes 49. tHA depends on which enable pin (CEL or R/WL) is deasserted first. 50. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
tRC READ 7FFE OR 1/3FFE)
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Ordering Information
4K x16 3.3V Asynchronous Dual-Port SRAM
Speed (ns) 15 20 Ordering Code CY7C024AV-15AI CY7C024BV-15AXI CY7C024AV-20AC CY7C024AV-20AXC CY7C024AV-20AI CY7C024AV-20AXI 25 CY7C024AV-25AC CY7C024AV-25AXC CY7C024AV-25AI CY7C024AV-25AXI Package Diagram 51-85048 51-85048 51-85048 51-85048 51-85048 51-85048 51-85048 51-85048 51-85048 51-85048 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack Industrial Commercial Industrial Commercial Operating Range Industrial
8K x16 3.3V Asynchronous Dual-Port SRAM
Speed (ns) 20 Ordering Code CY7C025AV-20AC CY7C025AV-20AXC CY7C025AV-20AXI 25 CY7C025AV-25AC CY7C025AV-25AXC CY7C025AV-25AI CY7C025AV-25AXI Package Name 51-85048 51-85048 51-85048 51-85048 51-85048 51-85048 51-85048 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack Industrial Industrial Commercial Operating Range Commercial
16K x16 3.3V Asynchronous Dual-Port SRAM
Speed (ns) 20 Ordering Code CY7C026AV-20AC CY7C026AV-20AXC CY7C026AV-20AXI 25 CY7C026AV-25AC CY7C026AV-25AXC CY7C026AV-25AI CY7C026AV-25AXI Package Name 51-85048 51-85048 51-85048 51-85048 51-85048 51-85048 51-85048 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack Industrial Industrial Commercial Operating Range Commercial
4K x18 3.3V Asynchronous Dual-Port SRAM
Speed (ns) 20 25 Ordering Code CY7C0241AV-20AC CY7C0241AV-25AC Package Name 51-85048 51-85048 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack Operating Range Commercial Commercial
8K x18 3.3V Asynchronous Dual-Port SRAM
Speed (ns) 20 25 Ordering Code CY7C0251AV-20AC CY7C0251AV-25AC Package Name 51-85048 51-85048 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack Operating Range Commercial Commercial
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16K x18 3.3V Asynchronous Dual-Port SRAM
Speed (ns) 20 25 Ordering Code CY7C036AV-20AC CY7C036AV-25AC CY7C036AV-25AXC CY7C036AV-25AI Package Name 51-85048 51-85048 51-85048 51-85048 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack Industrial Operating Range Commercial Commercial
Package Diagram
Figure 17. 100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100
51-85048 *C
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Document History Page
Document Title: CY7C024AV/024BV/025AV/026AV, CY7C0241AV/0251AV/036AV 3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM Document Number: 38-06052 Rev. ** *A *B *C *D *E *F ECN No. 110204 122302 128958 237622 241968 276451 279452 Orig. of Change SZV RBI JFU YDT WWZ SPN RUY Submission Date 11/11/01 12/27/02 9/03/03 See ECN See ECN See ECN See ECN Description of Change Change from Spec number: 38-00838 to 38-06052 Power up requirements added to Maximum Ratings Information Added CY7C025AV-25AI to Ordering Information Removed cross information from features section Added CY7C024AV-25AI to Ordering Information Corrected x18 for 026AV to x16 Added Pb-free packaging information Corrected pin A113L to A13L on CY7C026AV pin list Added minimum VIL of 0.3V and note 16 Corrected CY7C024AC-25AXC to CY7C024AV-25AXC in Ordering Information Added to Part Ordering information: CY7C024AV-15AI, CY7C024AV-15AXI, CY7C024AV-20AI, CY7C024AV-20AXI, CY7C025AV-20AXI, CY7C026AV-20AXI Updated note number 33 on page 12 from "R/W must be HIGH during all address transitions" to "R/W or CE must be HIGH during all address transitions" Added CY7C024BV part
*G *H
373580 380476
RUY PCX
See ECN See ECN
*I *J
2543577 2623540
NXR/AESA VKN/PYRS
07/25/08 12/17/08
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(c) Cypress Semiconductor Corporation, 2001-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-06052 Rev. *J
Revised December 10, 2008
Page 19 of 19
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